Journal Papers

2025

• S. Zheng, Z. Gao, F.-K. Sun, D. S. Boning, R. Rohrer, B. Yu, and M. D. F. Wong, “KirchhoffNet: End-to-End Analog Circuit Acceleration for ODE-Based Neural Networks,” submitted to IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, June 2025. **
• Z. Gao, J. Gu, L. Daniel, R. Rohrer, and D. Boning, “SPIPE: SPICE-Level Co-Simulation Program for Integrated Photonics and Electronics,” submitted to IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, June 2025. **
• P. Ma, Z. Yin, Q. Jing, Z. Gao, N. Gangi, B. Zhang, T.-W. Huang, Z. Huang, D. Boning, Y. Yao, and J. Gu, “SP²RINT: Spatially-Decoupled Physics-Inspired ProgRessive INverse OpTimization for Scalable, PDE-Constrained Meta-Optical Neural Network Training,” submitted to APL Photonics, May 2025. **
• F.-K. Sun, Y.-C. Wu, and D. S. Boning, “Simple Feedforward Neural Networks are Almost All You Need for Time Series Forecasting,” arXiv:2503.23621, March 2025. **
• Z. Gao, K. Zha, T. Zhang, Z, Xue, and D. S. Boning, “REG: Rectified Gradient Guidance for Conditional Diffusion Models,” arXiv:2501.18865, Jan. 2025. **

2024

• P. Ma, H. Yang, Z. Gao, D. Boning, and J. Gu, “PIC2O-Sim: A Physics-Inspired Causality-Aware Dynamic Convolutional Neural Operator for Ultra-Fast Photonic Device FDTD Simulation,” APL Photonics, vol. 10, no. 3, Mar. 2025. Also arXiv:2406.17810, June 2024. **
• Z. Gao, Z. Zhang, Z. He, J. Gu, D. Z. Pan, and D. S. Boning, “Selecting Robust Silicon Photonic Designs after Bayesian Optimization without Extra Simulations,” submitted to Optics Express, May 2024. **
• Z. Gao, X. Chen, Z. Zhang, U. Chakraborty, W. Bogaerts, and D. Boning, “Gradient-Based Power Efficient Functional Synthesis for Programmable Photonic Circuits,” accepted, Journal of Lightwave Technology, May 2024. **
• U. Chakraborty, D. Boning, and C. Thompson, “Bound-constrained Expectation Maximization for Failure Mode Identification in Weibull Competing-risks Device Reliability,” submitted to IEEE Trans. on Device and Material Reliability, April 2024. **

2023

• U. Chakraborty, E. Bender, D. Boning, and C. Thompson, “Identification of Multiple Failure Mechanisms for Device Reliability using Differential Evolution,” IEEE Trans. on Device and Material Reliability, vol. 23, no. 4, pp. 599-615, Dec. 2023. **
• Z. Gao, Z. Zhang, and D. S. Boning, “Few-Shot Bayesian Performance Modeling for Silicon Photonic Devices under Process Variation,” Journal of Lightwave Technology, vol. 41, no. 18, pp. 6007-6014, Sept. 2023.**
• Z. Zhang, S. I. El-Henawy, C. Rios, and D. S. Boning, “Inference of Process Variations in Silicon Photonics from Characterization Measurements,” Optics Express, vol. 31, no. 14, pp. 23651-23661, July 2023. **
• Z. Gao, X. Chen, Z. Zhang, U. Chakraborty, W. Bogaerts, and D. Boning, “Automatic Synthesis of Light Processing Functions for Programmable Photonics: Theory and Realization,” Photonics Research, vol. 11, No. 4, pp. 643-658, Optica, Apr. 2023. ** (Editors Highlight)
• Z. Zhang, M. Notaros, Z. Gao, U. Chakraborty, J. Notaros, and D. S. Boning, “Impact of Process Variations on Splitter-Tree-Based Integrated Optical Phased Arrays,” Optics Express, vol. 31, no. 8, pp. 12912-12921, April 2023. **
• Z. Gao, X. Chen, Z. Zhang, C.-Y. Lai, U. Chakraborty, W. Bogaerts, and D. Boning, “Provable Routing Analysis of Programmable Photonics,” Journal of Lightwave Technology, Apr. 2023.**

2022

• Z. Gao, X. Chen, Z. Zhang, U. Chakraborty, W. Bogaerts, and D. Boning, “Automatic Synthesis of Light Processing Functions for Programmable Photonics: Theory and Realization,” submitted to Photonics Research, Optica, Sept. 2022.
• E. Bender, J. B. Bernstein, and D. S. Boning, “Mitigation of Thermal Stability Concerns in FinFET Devices,” accepted, Electronics, Oct. 2022.
• Z. Gao, Z. Zhang, and D. S. Boning, “Automatic Synthesis of Broadband Silicon Photonic Devices via Bayesian Optimization,” submitted to Journal of Lightwave Technology, April 2022. **
• C. I. Lang, D. S. Boning, F.-K. Sun, B. Lawler, J. Dillon, A. Al Dujaili, J. Ruth, P. Cardillo, P. Alfred, A. Bowers, and A. McKiernan, “One Class Process Anomaly Detection Using Kernel Density Estimation Methods,” IEEE Trans. on Semiconductor Manufacturing, vol. 35, no. 3, pp. 457-469, Aug. 2022. **
• C. I. Lang, R. Sprenkle, E. Wilson, A. Samolov, and D. S. Boning, “Intelligent Optimization of Dosing Uniformity in Ion Implantation Systems,” IEEE Trans. on Semiconductor Manufacturing, vol. 35, no. 3, pp. 580-584, Aug. 2022. **
• C. I. Lang, F.-K. Sun, R. Veerasignam, J. Yamartino, and D. S. Boning, “Understanding and Improving Virtual Metrology Systems Using Bayesian Methods,” IEEE Trans. on Semiconductor Manufacturing, vol. 35, no. 3, pp. 511-521, Aug. 2022. **
• C. I. Lang, A. Jansen, S. Didari, P. Kothnur, and D. S. Boning, “Modeling and Optimizing the Impact of Process and Equipment Parameters in Sputtering Deposition Systems Using a Gaussian Process Machine Learning Framework,” IEEE Trans. on Semiconductor Manufacturing, vol. 35, no. 2, pp. 229-240, May 2022. **
• D. Boning, S. I. El-Henawy, and Z. Zhang, “Variation-Aware Methods and Models for Silicon Photonic Design-for-Manufacturability,” Journal of Lightwave Technology, vol. 40, no. 6, pp. 1776-1783, March 2022. **

2021

• K. Yeo, D. Grullon, F.-K. Sun, D. Boning, and J. Kalagnanam, “Variational inference formulation for a model-free simulation of a dynamical system with unknown parameters by a recurrent neural network,” SIAM Journal on Scientific Computing, Feb. 2021. **
• Z. Zhang, S. I. El-Henawy, A. Sadun, R. Miller, L. Daniel, J. K. White, and D. S. Boning, “Enabling Wavelength-Dependent Adjoint-Based Methods for Process Variation Sensitivity Analysis in Silicon Photonics,” Journal of Lightwave Technology, vol. 39, no. 6, pp. 1762-1769, March 2021. **

2020

• J. H. Lee, G. Traverso, D. Ibarra-Zarate, D. S. Boning, and B. W. Anthony, “Ex Vivo and In Vivo Imaging Study of Ultrasound Capsule Endoscopy,” Journal of Medical Devices, vol. 14, no. 2, 7 pp., June 2020. **

2019

• C. I. Lang and D. S. Boning, “Modeling and Controlling Layout Dependent Variations in Semi-Additive Copper Electrochemical Plating,” in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 4, pp. 366-373, Nov. 2019.
• C. I. Lang and D. S. Boning, “Modeling Spin Coating Over Topography and Uniformity Improvements Through Fill Patterns for Advanced Packaging Technologies,” in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 1, pp. 62-69, Feb. 2019.

2018

• J. H. Lee, D. S. Boning, and B. W. Anthony, “Measuring the Absolute Concentration of Microparticles in Suspension Using High-Frequency B-Mode Ultrasound Imaging,” Ultrasound in Medicine and Biology, vol. 44, no. 5, pp. 1086-1099, May 2018.

2016

• L. Yu, S. Saxena, C. Hess, I. A. M. Elfadel, D. A. Antoniadis and D. S. Boning, “Compact Model Parameter Extraction Using Bayesian Inference, Incomplete New Measurements, and Optimal Bias Selection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 7, pp. 1138-1150, July 2016.

2015

• W. H. Teh, D. S. Boning, and R. E. Welsch, “Multi-Strata Stealth Dicing Before Grinding for Singulation-Defects Elimination and Die Strength Enhancement: Experiment and Simulation,” IEEE Trans. on Semiconductor Manufacturing, vol. 28, no. 3, pp. 408-423, August 2015. **
• W. H. Teh, D. Boning, and R. Welsch, “Multi-strata subsurface laser die singulation to enable defect-free ultra-thin stacked memory dies,” AIP Advances, vol. 5, no. 5, paper 057128, June 2015. **
• W. H. Teh, D. S. Boning, and R. E. Welsch, “Multistrata Subsurface Laser-Modified Microstructure With Backgrind-Assisted Controlled Fracture for Defect-Free Ultrathin Die Fabrication,” IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 5, no. 7, pp. 1006-1018, August 2015. **
• H. Y. Boo, D. S. Boning, and H.-S. Lee,, “12b 250MS/S pipelined ADC with virtual ground reference buffers,” IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2912 – 2921, Sept. 2015. **

2013

• W. Zhang, K. Balakrishnan, X. Li, D. Boning, S. Saxena, A. Strojwas, and R. A. Rutenbar, “Efficient Spatial Pattern Analysis for Variation Decomposition via Robust Sparse Regression,” IEEE Trans. on Computer-Aided Design, vol. 32, no. 7, pp. 1072-1085, Jan. 2013. **

2011

• Drego, N., A. Chandrakasan, D. Boning, and D. Shah, “Reduction of Variation-Induced Energy Overhead in Multi-core Processors,” IEEE Transactions on Computer-Aided Design, vol. 30, no. 6, pp. 891-904, June 2011. **
• H. Taylor, K. Smistrup, and D. Boning, “Modeling and simulation of stamp deflections in nanoimprint lithography: exploiting backside grooves to enhance residual layer thickness uniformity,” Microelectronic Engineering, vol. 88, no. 8, pp. 2154-2157, August 2011. **
• H. Taylor, D. Boning, and C. Iliescu, “A razor-blade test of the demolding energy in a thermoplastic embossing process,” Journal of Micromechanics and Microengineering, vol. 21, no. 6, p. 067002, June 2011. **
• R. K. Jena, H. K. Taylor, Y. C. Lam, D. S. Boning, and C. Y. Yue, “Effect of polymer orientation on pattern replication in a micro-hot embossing process: experiments and numerical simulation,” Journal of Micromechanics and Microengineering, vol. 21, no. 6, p. 065007, June 2011. **

2010

• Drego, N., A. Chandrakasan, and D. Boning, “All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits,” IEEE Journal Solid-State Circuits, vol. 45, no. 3, pp. 640-651, March 2010.  **
• Fan, W., D. Boning, L. Charns, H. Miyauchi, H. Tano, and S. Tsuji, “Study on Hardness and Conditioning Effects of CMP Pad Based on Physical Die-level CMP Model,”  Journal of the Electrochemical Society, pp. H526-H533, vol. 157, no. 5, May 2010.  **
• Taylor, H., M. Hale, Y. C. Lam, and D. Boning, “A Method for the Accelerated Simulation of Micro-embossed Topographies in Thermoplastic Polymers,” Journal of Micromechanics and Microengineering, vol. 20, no. 6, p. 065001 (11 pp), June 2010. **
• Taylor, H., Y. C. Lam, and D. Boning, “An Investigation of the Detrimental Impact of Trapped Air in Thermoplastic Micro-embossing,” Journal of Micromechanics and Microengineering, vol. 20, no. 6, p. 065014 (12 pp), June 2010. **

2009

• Sampurno, Y., L. Borucki, Y. Zhuang, S. Misra, K. Holland, D. Boning, and A. Philipossian, “Characterization of Thermoset and Thermoplastic Polyurethane Pads, and Molded and Non-optimized Machined Grooving Methods for Oxide Chemical Mechanical Planarization Applications,” Thin Solid Films, vol. 517, no. 5, pp. 1719-1726, Jan. 2009.
• Xu, Z., S. Li, D. J. Burns, V. Shilpiekandula, H. K. Taylor, S. F. Yoon, K. Youcef-Toumi, I. Reading, Z. Fang, J. Zhao, and D. S. Boning, “Three-Dimensional Profile Stitching Based on the Fiducial Markers for Microfluidic Devices,” Optics Communications, February 2009. **
• Drego, N., A. Chandrakasasan, D. Boning, “Lack of Spatial Correlation in MOSFET Threshold Voltage Variation and Implications for Voltage Scaling,” IEEE Transactions on Semiconductor Manufacturing, vol. 22, no. 2, pp. 245-255, May 2009. **
• Taylor, H., Y.-C. Lam, and D. Boning, “A Computationally Simple Method for Simulating the Micro-embossing of Thermoplastic Layers,” Journal Micromechanics and Microengineering, vol. 19, no. 7, p. 075007 (16 pp), July 2009. **
• Xu, Z., H. K. Taylor, D. S. Boning, S. F. Yoon, and K. Youcef-Toumi, “Large-area and High-resolution Distortion Measurement Based on Moiré Fringe Method for Hot Embossing Process,” Optics Express, vol. 17, no. 21, pp. 18394-18407, Oct. 2009. **

2008

• Pham, H. T., S. F. Yoon, K. P. Chen, and D. Boning, “Characterization of carbon-doped InSb diode grown by molecular beam epitaxy,” Journal of Physics D: Applied Physics, vol. 41, no. 2, paper no. 025304, 6 pp., Jan. 2008. **
• Boning, D., K. Balakrishnan, H. Cai, N. Drego, A. Farahanchi, K. Gettings, D. Lim, A. Somani, H. Taylor, D. Truque, and X. Xie, “Variation,” IEEE Transactions on Semiconductor Manufacturing, vol. 21, no. 1, pp. 63-71, Feb. 2008. **
• Taylor, H., D. Boning, C. Iliescu, and B. Chen “Computationally efficient modeling of pattern dependencies in the micro-embossing of thermoplastic polymers,” Microelectronic Engineering, vol. 85, no. 5-6, pp. 1453-1456,  May-June, 2008. **
• Gettings, K. and D. Boning, “Study of CMOS Process Variation by Multiplexing Analog Characteristics,” IEEE Transactions on Semiconductor Manufacturing, vol. 21, no. 4, pp. 513-525, Nov. 2008. **

2007

• Pham, H. T., S. F. Yoon, D. Boning, and S. Wicaksono, “Molecular beam epitaxial growth of indium antimonide and its characterization,” Journal of Vacuum Science and Technology B, vol. 25, no. 1, pp. 11-16, Jan./Feb. 2007. **
• Pham, H. T., S. F. Yoon, K. H. Tan, and D. Boning, “Effects of nitrogen incorporation in InSb1-xNx grown using radio frequency plasma-assisted molecular beam epitaxy,” Applied Physics Letters, vol. 90, pp. 092115-1 to 092115-3, February 2007. **
• Abrokwah, K. O., P. R. Chidambaram, and D. S. Boning, “Pattern Based Prediction for Plasma Etch,” IEEE Transactions on Semiconductor Manufacturing, vol. 20, no. 2, pp. 77-86, May 2007. **

2006

• Taylor, H. K., H. Sun, T. F. Hill, A. Farahanchi, and D. S. Boning, “Characterizing and Predicting Spatial Non-uniformity in the Deep Reactive Ion Etching of Silicon,” Journal of the Electrochemical Society, vol. 153, no. 8, pp. C575-C585, June 2006. **

2005

• Sampurno, Y., L. Borucki, Y. Zhuang, D. Boning, and A. Philipossian, “A Method for Direct Measurement of Substrate Temperature During Copper CMP,” Journal of the Electrochemical Society, vol. 152, no. 7, pp. G537-G541, July 2005.  **
• Tang, B. D., X. L. Xie, and D. S. Boning, “Damascene Chemical-Mechanical Polishing Characterization and Modeling for Polysilicon Microelectromechanical Systems Structures,” Journal of the Electrochemical Society, vol. 152, no. 7, pp. G582-G587, July 2005. **
• Li, Z., P. Lefevre, I. Koshiyama, K. Ina, D. Boning, and A. Philipossian, “Comparison of Copper Disc and Copper Wafer Polishing Processes in Terms of Their Kinetic, Tribological and Thermal Characteristics,” IEEE Transactions on Semiconductor Manufacturing, vol. 18, no. 4, pp. 681-687, Nov. 2005. **

2004

• Sorooshian, J., D. DeNardis, L. Charns, Z. Li, F. Shadman, D. Boning, D. Hetherington, and A. Philipossian, “Arrhenius Characterization of ILD and Copper CMP Processes,” Journal of the Electrochemical Soci­ety, vol. 151, no. 2, pp. G85-G88, Feb. 2004. **
• Park, T., T. Tugbawa, D. Boning, C. Chidambaram, C. Borst, and G. Shin, “Chip-Scale Modeling of Electroplated Copper Surface Profiles,” Journal of the Electrochemical Society, vol. 151, no. 6, pp. C418-C430, June 2004. **
• Sorooshian, J., L. Borucki, R. Timon, D. Stein, D. Boning, D. Hetherington, and A. Philipossian, “Estimating the Effective Pressure on Patterned Wafers during STI CMP,” Electrochemical and Solid State Letters, vol. 7, no. 10, pp. G204-G206, Oct. 2004. **

2003

• White, D., J. Melvin, and D. Boning, “Characterization and Modeling of Dynamic Thermal Behav­ior in CMP,” Journal of the Electrochemical Soci­ety, vol. 150, no. 4, pp. G271-G278, April 2003. **
• Goodlin, B. E., D. S. Boning, H. H. Sawin, and B. M. Wise, “Simultaneous Fault Detection and Classification for Semiconductor Manufacturing Tools,” Journal of the Electrochemical Society, vol. 150, no. 12, pp. G778-G784, Dec. 2003. **

2002

• Ouma, D. O., D. S. Boning, J. E. Chung, W. G. Easter, V. Saxena, S. Misra, and A. Crevasse, “Char­acterization and Modeling of Oxide Chemical Mechanical Polishing Using Planarization Length and Pattern Density Concepts,” IEEE Transactions on Semiconductor Manufacturing, vol. 15, no. 2, pp. 232-244, May 2002. **
• Gower, A., D. Boning, P. Rosenthal, and A. Waldhauer, “Model-Based Uniformity Control for Epi­taxial Silicon Deposition,” IEEE Transactions on Semiconductor Manufacturing, vol. 15, no. 3, pp. 295-309, August 2002. **

2001

• Gan, T., T. Tugbawa, B. Lee, D. Boning, and S. Jang, “Modeling of Reverse Tone Etchback Shal­low Trench Isolation Chemical Mechanical Polishing,” Journal of the Electrochemical Society, vol. 148, no. 3, pp. G159-G165, March 2001. **

2000

• White, D., B. Goodlin, A. Gower, D. Boning, H. Chen, H. Sawin, and T. Dalton, “Low-Open Area Endpoint Detection using a PCA based T2 Statistic and Q Statistic on Optical Emission Spectros­copy Measurements,” IEEE Transactions on Semiconductor Manufacturing, vol. 13, no. 2, pp. 193-207, May 2000. **
• Oji, C., B. Lee, D. Ouma, T. Smith, J. Yoon, J. Chung, and D. Boning, “Wafer Scale Variation of Planarization Length in Chemical Mechanical Polishing,” Journal of the Electrochemical Society, vol. 147, no. 11, pp. 4307-4312, Nov. 2000. **

1999

• Smith, T., S. J. Fang, J. A Stefani, G. B. Shinn, D. S. Boning, and S. W. Butler, “On-line Patterned Wafer Thickness Control of Chemical-Mechanical Polishing,” Journal of Vacuum Science and Technology A, vol. 17, no. 4, pp. 1384-1390, July/Aug. 1999.**
• Smith, T., B. E. Goodlin, D. Boning, and H. H. Sawin, “A Statistical Analysis of Single and Mul­tiple Response Surface Modeling,” IEEE Transactions on Semiconductor Manufacturing, vol. 12, no. 4, pp. 419-430, Nov. 1999. **

1998

• Stine, B., D. Ouma, R. Divecha, D. Boning, J. Chung, D. Hetherington, C. R. Harwood, O. S. Na­kagawa, and S.-Y. Oh, “Rapid Characterization and Modeling of Pattern Dependent Variation in Chemical Mechanical Polishing,” IEEE Transactions on Semiconductor Manufacturing, vol. 11, no. 1, pp. 129-140, Feb. 1998. **
• Stine, B., D. Boning, J. Chung, L. Camilletti, F. Kruppa, E. Equi, W. Loh, S. Prasad, M. Muth­ukrishnan, D. Towery, M. Berman, and A. Kapoor, “The Physical and Electrical Effects of Metal Fill Patterning Practices for Oxide Chemical Mechanical Polishing Processes,” IEEE Transactions on Electron Devices, vol. 45, no. 3, pp. 665-679, March 1998. **
• Divecha, R., B. Stine, D. Ouma, E. Chang, D. Boning, J. Chung, O. S. Nakagawa, H. Aoki, G. Ray, D. Bradbury, and S.-Y. Oh, “A Novel Statistical Metrology Framework for Identifying Sources of Variation in Oxide Chemical Mechanical Polishing,” Journal of the Electrochemical Society, vol. 145, no. 3, pp. 1052-1059, March 1998. **
• Smith, T., D. Boning, J. Stefani, and S. W. Butler, “Run by Run Advanced Process Control of Metal Sputter Deposition,” IEEE Transactions on Semiconductor Manufacturing, vol. 11, no. 2, pp. 276 -284, May 1998. **
• Stine, B., D. Boning, J. Chung, D. Ciplickas, and J. Kibarian, “Simulating the Impact of Poly-CD Wafer-Level and Die-Level Variation On Circuit Performance,” IEEE Transactions on Semicon­ductor Manufacturing, vol. 11, no. 4, pp. 552-556, Nov. 1998. **

1997

• McIlrath, M. B., D. S. Boning, and D. E. Troxel, “Towards an Architecture for Distributed Design and Fabrication of Semiconductors,” International Journal of Agile Manufacturing, Oct. 1997. **
• Prasad, S., W. Loh, A. Kapoor, E. Chang, B. Stine, D. Boning, and J. Chung, “Statistical Metrology for Characterizing CMP Processes,” Microelectronic Engineering, vol. 33, pp. 231-240, Jan. 1997. **
• Smith, T. and D. Boning, “Artificial Neural Network Exponentially Weighted Moving Average Controller for Semiconductor Processes,” Journal of Vacuum Science and Technology A, vol. 15, no. 3, pp. 1377-1384, May/June 1997. **
• Smith, T., A. Gower, and D. Boning, “A matrix math library for Java,” Concurrency: Practice and Experience, vol. 9, no. 11, pp. 1127-1137, Nov. 1997. **
• Smith, T., and D. Boning, “A Self-Tuning EWMA Controller Utilizing Artificial Neural Network Function Approximation Techniques,” IEEE Transactions on Components, Packaging, and Manufactur­ing Technology – Part C, vol. 20, no. 2, pp. 121-132, Apr. 1997. **
• Stine, B., D. Boning, and J. Chung, “Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices,” IEEE Transactions on Semiconductor Manufacturing, pp. 24-41, Feb. 1997. **
• White, D., D. Boning, S. Butler, and G. Barna, “Spatial Characterization of Wafer State using Prin­cipal Component Analysis of Optical Emission Spectra,” IEEE Transactions on Semiconductor Manufacturing, pp. 52-61, Feb. 1997. **
• Wong, K.S., D. Boning. H. Sawin, S. Butler, and E. Sachs, “Endpoint prediction for polysilicon plasma etching via optical emission interferometry,” Journal of Vacuum Science and Technology A, vol. 15, no. 3, pp. 1403-1408, May/June 1997. **

1996

• Boning, D., A. Hurwitz, J. Moyne, W. Moyne, S. Shellman, T. Smith, J. Taylor, and R. Telfeyan, “Run by Run Control of Chemical Mechanical Polishing,” IEEE Transactions on Components, Packaging, and Manufacturing Technology – Part C, vol. 19, no. 1, pp. 307-314, Oct. 1996. **
• Telfeyan, R., J. Moyne, N. Chaudhry, J. Pugmire, S. Shellman, D. Boning, W. Moyne, A. Hurwitz, and J. Taylor, “A Multi-Level Approach to the Control of a Chemical-Mechanical Planarization Process,” Journal of Vacuum Science and Technology A, pp. 1907-1913, May/June 1996. **

1995

• Yu, C., T. Maung, C. Spano s, D. Boning, J. Chung, H.-Y. Liu, K.-J. Chang, and D. Bartelink, “Use of Short-Loop Electrical Measurements for Yield Improvement,” IEEE Transactions on Semiconductor Manufacturing, pp. 150-159, May 1995. **

1994

• Boning, D. and P. Mozumder, “DOE/Opt: A System for Design of Experiments, Response Surface Modeling, and Optimization using Process and Device Simulation,” IEEE Transactions on Semiconductor Manufacturing, pp. 233-244, Jan. 1994.
• Giles, M. D., D. S. Boning, G. R. Chin, W. C. Dietrich, M. S. Karasick, M. E. Law, P. K. Mozum­der, L. R. Nackman, V. T. Rajan, D. M. H. Walker, R. H. Wang, and A. S. Wong, “Semiconductor Wafer Representation for TCAD,” IEEE Transactions Computer Aided Design, pp. 82-95, Jan. 1994.

1993

• D. Durbeck, J.-H. Chern, and D. S. Boning, “A System for Semiconductor Process Specification,” IEEE Transactions on Semiconductor Manufacturing, pp. 297-305, Nov. 1993.
• Gopalarao, K., P. Mozumder, and D. Boning, “An Integrated Technology CAD System for Process and Device Designers,” IEEE Transactions VLSI Systems, pp. 482-490, Dec. 1993.

1992

• Boning, D. S., M. B. McIlrath, P. Penfield, Jr., and E. M. Sachs, “A General Semiconductor Process Modeling Framework,” IEEE Transactions on Semiconductor Manufacturing, pp. 266-280, Nov. 1992.
• McIlrath, M. B., D. E. Troxel, D. S. Boning, M. L. Heytens, and P. Penfield, Jr., “CAFE – The  M.I.T. Computer-Aided Fabrication Environment,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, pp. 353-360, June 1992.

1991

• Boning, D. S., M. L. Heytens, and A. S. Wong, “The Intertool Profile Interchange Format: An Ob­ject Oriented Approach,” IEEE Transactions on Computer Aided Design, pp. 1150-1156, Sept. 1991.

1988

• Boning, D. S., and D. A. Antoniadis, “A Workstation Approach to IC Process and Device Design,” IEEE Design and Test of Computers, pp. 36-47, April, 1988.

** Outgrowth of supervised student research